In the manufacture of an electronic device having an element such as, for example, a fin-type field effect transistor, a SAC (Self-Aligned Contact) process is used to form a contact.
A workpiece to be subjected to the SAC process includes a base layer, two raised regions, a nitride region and an oxide region. The base layer is, e.g., a polycrystalline silicon layer. The two raised regions are, e.g., gates, and are formed of polycrystalline silicon. These raised regions are provided on the base layer to be spaced apart from each other. The nitride region is made of silicon nitride and is provided so as to cover the two raised regions and the base layer. The oxide region is made of silicon oxide and is provided so as to cover the nitride region.
In the SAC process, a hole is formed in the oxide region to extend from the surface of the oxide region to the base layer via a region between the two raised regions. Generally, in the SAC process, in order to form such an opening, the oxide region is etched and the nitride region adjoining the base layer is etched using plasma of a fluorocarbon gas. Japanese Patent Laid-Open Publication No. 2000-307001 discloses such an SAC process.